1. Field of the Invention
The present invention relates to the physical design of integrated circuits, especially analog integrated circuits, and more particularly, to the improved automation of integrated circuit design.
2. Description of Related Art
Heretofore, the physical design of integrated circuits (ICs), especially Analog ICs, was a time-consuming and labor-intensive task. The complexity of analog circuit layout comes from the extreme sensitivity of the continuous analog signal over the device interaction, fabrication process and operating environment, which require fine tuning of the physical circuit layout. To minimize these degrading influences on IC performance, analog layout engineers adopt various geometrical techniques such as, without limitation: interdigitation, device merging, matching, symmetrical layout, guard ring protection, etc. How these techniques are applied to the layout is mostly dependent on the designer's experience. Multiple iterations between simulation, schematic design and layout design are common practice to meet the design specification.
Physical circuit layout is not usually done from scratch, but instead using a hierarchical design library of scalable components and different types of “sub circuits,” thereby saving a great deal of labor. A “sub circuit” is a fragment of a circuit that has defined interface nodes (or equivalently, “terminals” or “pins”) to other circuits or other sub circuits, that may occur repeatedly, sometimes with different component scaling, in a circuit design. Sub circuits may be more or less complex. Examples of sub circuits that an analog or mixed-signal circuit designer may deal with at low-levels can include, without limitation: differential transistor pairs; parallel connections of transistors in different common node configurations (e.g., common gate, source, or drain configuration for field effect transistors “FETs”; or common emitter, base, or collector configuration for bipolar junction transistors “BJTs”); cascode transistor pairs; current mirrors; cascode current mirrors; and the like.
The general approach of layout generation is, first partition the schematic into predefined more or less complex modules, then place and route these modules by deterministic or nonlinear optimization algorithms. In the common analog design methodology, dedicated module libraries or module generators are used to create layout instances. Although the number of module types is usually limited in the analog design domain (for example, current mirror, differential pair, diode-connected transistor, etc.), the creation of technology-independent parameterized modules is very complicated and time-consuming. The difficulty comes from the great number of variants of the modules' layout topology, connectivity, technology dependency, and device dimension. It is not unusual to find hundreds of parameter settings or complex language programming needed for module generation tools. The steep learning curve and low maintainability seriously limit the adoption of those tools in industry.
It would, therefore, be desirable to overcome the above problem(s) and others by providing an apparatus and method to generate circuit (or sub circuit) designs more easily and efficiently and to be able to reuse such circuit designs more readily.